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Shouri Chatterjee : Curriculum Vitae
Journal publications
[1]
H. Shrimali and S. Chatterjee, “A technique to linearize the discrete-time parametric amplifier,” Microelectronics Journal, vol. 46, no. 11, pp. 1033–1038, Nov. 2015.
[2]
G. Chowdary and S. Chatterjee, “A 300-nW Sensitive, 50-nA DC-DC Converter for Energy Harvesting Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 11, pp. 2674–2684, Nov. 2015.
[3]
K. A. Fante, B. Bhaumik, and S. Chatterjee, “Design and Implementation of Computationally Efficient Image Compressor for Wireless Capsule Endoscopy,” Circuits Syst Signal Process, pp. 1–27, Aug. 2015.
[4]
H. Shrimali and S. Chatterjee, “Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 12, pp. 902–905, Dec. 2011.
[5]
N. Nallam and S. Chatterjee, “Multi-Band Frequency Transformations, Matching Networks and Amplifiers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1635–1647, Jun. 2013.
[6]
S. Chatterjee, Y. Tsividis, and P. Kinget, “Ultra-Low Voltage Analog Integrated Circuits,” IEICE TRANSACTIONS on Electronics, vol. E89–C, no. 6, pp. 673–680, Jun. 2006.
[7]
S. Chatterjee and P. R. Kinget, “A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 722–729, Apr. 2007.
[8]
K.-P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC,” IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 496–507, Mar. 2007.
[9]
S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2373–2387, 2005.
Conference publications
[1]
K. A. Fante, B. Bhaumik, and S. Chatterjee, “A Low-Power Color Mosaic Image Compressor Based on Optimal Combination of 1-D Discrete Wavelet Packet Transform and DPCM for Wireless Capsule Endoscopy:,” in Proceedings of the International Conference on Biomedical Electronics and Devices, Lisbon, Portugal, 2015, pp. 190–197.
[2]
B. Bhuvan, S. Chatterjee, and M. Sarkar, “PTC Inspired Column Level Compression in Low Power CMOS Imagers,” in 2015 International Image Sensors workshop, Vaals, The Netherlands, 2015.
[3]
N. Nallam and S. Chatterjee, “On the use of frequency transformations in the design of broad-band and concurrent multi-band power amplifiers,” in 2015 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), 2015, pp. 1–3.
[4]
S. Monga and S. Chatterjee, “A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 um CMOS.,” in System-on-Chip Conference (SOCC), 2014 27th IEEE International, 2014, pp. 431–436.
[5]
S. Monga and S. Chatterjee, “An inductorless continuous time equalizer with programmability for gigabit links,” in 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014, pp. 713–716.
[6]
S. Monga and S. Chatterjee, “An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 450–454.
[7]
S. Kundu and S. Chatterjee, “A 44 GHz Quadrature Traveling Wave Oscillator,” in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013, pp. 179–184.
[8]
P. Dubey, D. Belot, and S. Chatterjee, “Heterogeneous coupled ring oscillator arrays for reduced phase noise at lower power consumption,” in Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian, 2012, pp. 365–368.
[9]
H. Shrimali and S. Chatterjee, “Third order harmonic cancellation technique for a parametric amplifier,” in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 1880–1883.
[10]
S. De, A. Kawatra, and S. Chatterjee, “On the Feasibility of Network RF Energy Operated Field Sensors,” in 2010 IEEE International Conference on Communications (ICC), 2010, pp. 1–5.
[11]
S. Kumar and S. Chatterjee, “A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time Sigma Delta Modulator for Audio Applications,” in 2012 25th International Conference on VLSI Design (VLSID), 2012, pp. 51–56.
[12]
H. Shrimali and S. Chatterjee, “11 GHz UGBW Op-amp with feed-forward compensation technique,” in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 17–20.
[13]
N. Nallam and S. Chatterjee, “Design of concurrent multi-band matching networks,” in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 201–204.
[14]
P. Kinget, S. Chatterjee, and Y. Tsividis, “Ultra-Low Voltage Analog Design Techniques for Nanoscale CMOS Technologies,” in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, 2005, pp. 9–14.
[15]
S. Chatterjee and P. Kinget, “A 0.5-V 1-Msample/s 60-dB SNDR Track-and-Hold Circuit,” in 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, pp. 45–46.
[16]
K.-P. Pun, S. Chatterjee, and P. Kinget, “A 0.5V 74dB SNDR 25kHz CT Delta Sigma Modulator with Return-to-Open DAC,” in Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, 2006, pp. 181–190.
[17]
S. Chatterjee, T. Musah, Y. Tsividis, and P. Kinget, “Weak inversion MOS varactors for 0.5 V analog integrated filters,” in 2005 Symposium on VLSI Circuits, 2005. Digest of Technical Papers, 2005, pp. 272–275.
[18]
S. Chatterjee, Y. Tsividis, and P. Kinget, “A 0.5-V bulk-input fully differential operational transconductance amplifier,” in Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 2004, pp. 147–150.
[19]
S. Chatterjee, Y. Tsividis, and P. Kinget, “A 0.5V filter with PLL-based tuning in 0.18 um CMOS,” in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005, pp. 506–613 Vol. 1.
[20]
H. S. Bindra, S. Chatterjee, K. Saha, and T. Kukal, “Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation,” in 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2472–2475.
Patents
[1]
J. S. Madsen, S. Chatterjee, and P. A. Lagervall, “Serial data interface,” US6952174 B2, 04-Oct-2005.
[2]
S. Chatterjee, P. R. Kinget, and Y. Tsividis, “Low voltage operational transconductance amplifier circuits,” US8030999 B2, 04-Oct-2011.
[3]
K.-P. Pun, S. Chatterjee, and P. R. Kinget, “Low voltage digital to analog converter, comparator and sigma-delta modulator circuits,” US8305247 B2, 06-Nov-2012.
[4]
K.-P. Pun, S. Chatterjee, and P. R. Kinget, “Low voltage comparator circuits,” US8704553 B2, 22-Apr-2014.
[5]
S. Chatterjee and P. R. Kinget, “Low voltage track and hold circuits,” US8441287 B2, 14-May-2013.
[6]
S. Chatterjee, A. Eshraghi, and J. Khoury, “Performing automatic frequency control,” US20080132178 A1, 05-Jun-2008.
Books and chapters
[1]
S. De and S. Chatterjee, “Network Energy Driven Wireless Sensor Networks,” in Biologically Inspired Networking and Sensing: Algorithms and Architectures, P. Lio and D. Verma, Eds. IGI Global, 2012.
[2]
P. Kinget, S. Chatterjee, and Y. Tsividis, “0.5 V ANALOG INTEGRATED CIRCUITS,” in Analog Circuit Design, M. Steyaert, J. H. Huijsing, and A. H. M. van Roermund, Eds. Springer Netherlands, 2006, pp. 329–350.
[3]
S. Chatterjee, K. P. Pun, N. Stanic, Y. Tsividis, and P. Kinget, Analog Circuit Design Techniques at 0.5V. Springer, 2010.