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Title	Added By	Updated On
Energy-efficient SRAM design in 28nm FDSOI Technology	even.laate	Oct 31, 2014 4:59:01 PM
280mV sense amplifier designed in 28nm UTBB FD-SOI technology using back-biasing control	even.laate	Oct 29, 2014 9:56:46 AM
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test	even.laate	Oct 29, 2014 8:22:54 AM
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology	even.laate	Oct 27, 2014 8:34:15 AM
Design of a robust and ultra-low-voltage pulse-triggered flip-flop in 28nm UTBB-FDSOI technology	even.laate	Oct 23, 2014 3:16:25 PM
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control	even.laate	Oct 22, 2014 4:34:23 PM
UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency	even.laate	Oct 22, 2014 3:07:37 PM
Ultra low power SoC	even.laate	Oct 14, 2014 2:26:10 PM
Advancements in Low Power with Professor Chandrakasan (MIT)	even.laate	Oct 14, 2014 2:14:32 PM
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial	even.laate	Oct 13, 2014 12:02:28 PM

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This group is intended for sharing of research references within the field of subthreshold CMOS design.

Owner: even.laate
Registered: 2014-10-06
Type: Public
Membership: Open

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